Device/Circuit/Architectural Techniques for Ultra-low Power FPGA Design

Field Programmable Gate Arrays (FPGAs) are widely used for implementation of dig ital system design due to their flexibility, low time-to-market, growing density and speed. But the Power consumption, especially leakage and dynamic power has become a major concern for semiconductor industries. FPGAs are less power-efficient than custom ASICs, due to the overhead required to provide programmability. Despite this, power has been largely ignored by the FPGA research community earlier, whose prime focus centred on improving FPGA speed and area -efficiency. But nowadays research extensively focuses on power too. Hence this paper demonstrates so me of the most utilized and efficient techniques for Power optimizat ion and reduction in FPGAs currently. After reviewing latest research work on power reduction in FPGA we examined that using Dual VT and fine-grained VDD static power reduces upto 64% and 95% respectively. Clock Gat ing reduces the power consumption by the factor 50% and also by using latest novel devices like Tunnel FET power can be reduced much lower than present .